پردازنده دو هسته ای TMS320F28379DPTPT برد لانچپد

توضیحات
نظرات کاربران
برچسب ها

پردازنده دو هسته ای TMS320F28379DPTPT برد لانچپد

Features

Dual-Core Architecture
- Two TMS320C28x 32-Bit CPUs
- 200 MHz
- IEEE 754 Single-Precision Floating-Point Unit (FPU)
- Trigonometric Math Unit (TMU)
- Viterbi/Complex Math Unit (VCU-II)
Two Programmable Control Law Accelerators (CLAs)
- 200 MHz
- IEEE 754 Single-Precision Floating-Point Instructions
- Executes Code Independently of Main CPU
On-Chip Memory
- 512KB (256KW) or 1MB (512KW) of Flash (ECC-Protected)
- 172KB (86KW) or 204KB (102KW) of RAM (ECC-Protected or Parity-Protected)
- Dual-Zone Security Supporting Third-Party Development
Clock and System Control
- Two Internal Zero-Pin 10-MHz Oscillators
- On-Chip Crystal Oscillator
- Windowed Watchdog Timer Module
- Missing Clock Detection Circuitry
1.2-V Core, 3.3-V I/O Design
System Peripherals
- Two External Memory Interfaces (EMIFs) With ASRAM and SDRAM Support
- Dual 6-Channel Direct Memory Access (DMA) Controllers
- Up to 169 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering
- Expanded Peripheral Interrupt Controller (ePIE)
- Multiple Low-Power Mode (LPM) Support With External Wakeup
Communications Peripherals
- USB 2.0 (MAC + PHY)
- Support for 12-Pin 3.3 V-Compatible Universal Parallel Port (uPP) Interface
- Two Controller Area Network (CAN) Modules (Pin-Bootable)
- Three High-Speed (up to 50-MHz) SPI Ports (Pin-Bootable)
- Two Multichannel Buffered Serial Ports (McBSPs)
- Four Serial Communications Interfaces (SCI/UART) (Pin-Bootable)
- Two I2C Interfaces (Pin-Bootable)
Analog Subsystem
- Up to Four Analog-to-Digital Converters (ADCs)
  - 16-Bit Mode
    - 1.1 MSPS Each (up to 4.4-MSPS System Throughput)
    - Differential Inputs
    - Up to 12 External Channels
  - 12-Bit Mode
    - 3.5 MSPS Each (up to 14-MSPS System Throughput)
    - Single-Ended Inputs
    - Up to 24 External Channels
  - Single Sample-and-Hold (S/H) on Each ADC
  - Hardware-Integrated Post-Processing of ADC Conversions
    - Saturating Offset Calibration
    - Error From Setpoint Calculation
    - High, Low, and Zero-Crossing Compare, With Interrupt Capability
    - Trigger-to-Sample Delay Capture
- Eight Windowed Comparators With 12-Bit Digital-to-Analog Converter (DAC) References
- Three 12-Bit Buffered DAC Outputs
Enhanced Control Peripherals
- 24 Pulse Width Modulator (PWM) Channels With Enhanced Features
- 16 High-Resolution Pulse Width Modulator (HRPWM) Channels
  - High Resolution on Both A and B Channels of 8 PWM Modules
  - Dead-Band Support (on Both Standard and High Resolution)
- Six Enhanced Capture (eCAP) Modules
- Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
- Eight Sigma-Delta Filter Module (SDFM) Input Channels, 2 Parallel Filters per Channel
  - Standard SDFM Data Filtering
  - Comparator Filter for Fast Action for Out of Range